Title :
Region definition for minimizing the number of switchboxes and ordering assignment
Author :
Yan, Jin-Tai ; Hsiao, Pei-Yung
Author_Institution :
Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
30 May-2 Jun 1994
Abstract :
For a building block placement, the routing space can be partitioned into channels and switchboxes. The definition of switchboxes can release the cyclic channel precedence constraints and further yield a safe routing ordering process. However, switchbox routing is always more difficult than channel routing. In this paper, an O(nlogN) region definition and ordering assignment algorithm is proposed to minimize the number of switchboxes, where N is the number of vertices in a channel precedence graph. Several examples have been tested on this algorithm, the experimental results are listed and compared
Keywords :
VLSI; circuit layout CAD; graph theory; integrated circuit layout; network routing; network topology; VLSI; building block placement; channel precedence graph; cyclic channel precedence constraints; layout design; ordering assignment; region definition; routing space; safe routing ordering process; switchboxes; Compaction; Information science; Partitioning algorithms; Quantum cascade lasers; Routing; Testing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408766
