190V N-channel lateral IGBT integration in SOI 0.35 µm BCD technology

Author

Sambi, M. ; Gallo, M. ; Galbiati, P.

Author_Institution

STMicroelectronics TRD, Agrate Brianza

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

The integration of 190 V N-Ch. ateral IGBT in SOI 0.35 mum shrunk BCD technology is described in this paper. LIGBT design optimization by simulation and silicon characterization data are here reported, highlighting the superior current capability of LIGBT with respect to equivalent power MOS. Behavior during high temperature reverse bias (HTRB) test was investigated and basic IGBT structure modified to minimize the stress induced effects. The novel device shows a very high saturation current (around 2.5 kA cm^-2) and excellent electrical parameter stability after HTRB stress test.

Keywords

BIMOS integrated circuits; insulated gate bipolar transistors; integrated circuit design; integrated circuit modelling; integrated circuit testing; optimisation; power integrated circuits; power semiconductor devices; semiconductor device models; semiconductor device testing; silicon-on-insulator; stress effects; HTRB stress test; LIGBT design optimization; N-channel lateral IGBT integration; SOI 0.35 mum BCD technology; Si; electrical parameter stability; high temperature reverse bias test; power MOS; saturation current; shrunk BCD technology; size 0.35 micron; superior current capability; voltage 190 V; Dielectric substrates; Driver circuits; Electrostatic discharge; Insulated gate bipolar transistors; Isolation technology; Plasma displays; Portfolios; Silicon; Stress; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796633

Filename

4796633