Approximate computation of signal characteristics of on-chip RC interconnect trees

Fast and efficient computation of signal characteristics such as delay, slew etc. play a key role in design and analysis of high performance VLSI circuits. Elmore approximation may not be accurate when resistive components of the interconnect significantly affect signal characteristics. An efficient mechanism to compute the driving point admittance of a resistive interconnect tree exists, in which the tree is traversed bottom-up to compute the driving point admittance (DPA). An approximation technique is proposed in this paper which involves traversing an interconnect RC tree top-down to compute the signal characteristics, by exploiting already calculated admittance at every node. A piecewise linear approximation obtained from the analytical expression for voltage at every node is used to compute voltages at subsequent nodes in the tree. The advantage of the proposed technique is efficient and fast computation of interconnect signal characteristics from already computed admittance information. Results comparing the proposed technique with RICE and Elmore on representative RC trees of antifuse based FPGA interconnect are presented