Statistical constrained optimization of analog MOS circuits using empirical performance models

In this paper, we present a statistical constrained CAD-compatible optimization algorithm for analog MOS integrated circuit design. The algorithm uses design of experiments (DOE), together with the response surface methodology (RSM), to determine simple empirical models relating circuit performances to device sizes. It then applies the Lagrange multiplier method to solve the resulting statistical constrained nonlinear optimization problem. The algorithm is guaranteed to converge to the global minimum. Using this new algorithm, we show that the transistors which cause variations in the performances of a two-stage op-amp can be identified and resized in an area-efficient manner to meet performance specifications