Title :
Worst case design of digital integrated circuits
Author_Institution :
Dept. of Res. & Dev., Western Atlas Inc., Houston, TX, USA
fDate :
30 May-2 Jun 1994
Abstract :
This paper describes ±σ transistor modeling and its application in worst case design of digital integrated circuits. We explore the implicit assumptions made when using the ±σ transistor model, establish the relationship between worst-case design and variability minimization, and extend the variability minimization principles to the worst-case measure reduction. A CMOS delay circuit is used to clarify the discussion
Keywords :
circuit optimisation; digital integrated circuits; integrated circuit design; integrated circuit modelling; minimisation; semiconductor device models; IC design; digital integrated circuits; sigma transistor modeling; worst-case design; worst-case measure reduction; Computational efficiency; Computer aided software engineering; Current measurement; Delay; Digital integrated circuits; Integrated circuit modeling; Minimization; Semiconductor device modeling; Transistors; Voltage;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408778
