Title :
A stochastic reward and punishment neural network algorithm for circuit bipartitioning
Author :
Unaltuna, M. Kemal ; Pitchumani, Vijay
Author_Institution :
Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
fDate :
30 May-2 Jun 1994
Abstract :
Circuit bipartitioning is an NP-hard combinatorial optimization problem in the layout synthesis of VLSI circuits, where we wish to find a partition of the circuit elements into two blocks such that the number of signal nets crossing the partition boundary is minimized. We have developed and experimented with several competitive learning neural network algorithms to solve this problem. The algorithms were tested on randomly generated circuits as well as several popular benchmark circuits. The stochastic reward and punishment neural network produced the best results which were comparable to those found by the Ratio Cut algorithm of Wei and Cheng
Keywords :
VLSI; circuit layout CAD; circuit optimisation; computational complexity; integrated circuit layout; logic CAD; logic partitioning; neural nets; unsupervised learning; NP-hard combinatorial optimization problem; VLSI circuits; benchmark circuits; circuit bipartitioning; circuit elements; competitive learning; layout synthesis; neural network algorithm; partition boundary; randomly generated circuits; signal nets; stochastic reward and punishment network; Benchmark testing; Circuit synthesis; Circuit testing; Fires; Network synthesis; Neural networks; Partitioning algorithms; Signal synthesis; Stochastic processes; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408785
