Automatic functional cell generation in the sea-of-gates layout style

With a logic circuit as an input, the transistors in the circuit are first placed on a sea-of-gates template by a newly developed simulated annealing placement method. The transistors are then interconnected as required using the wires available in two metal layers. For this, we developed a novel three phase routing strategy which consists of global routing, channel routing and final detailed routing. The shape of the generated cells is a rectangle with adjustable width and height. The areas of the cells are minimum and the use of the second metal wires is minimized. Experimental results for many test circuits are very satisfying and the time needed is acceptable