CUPLAND-a behavioral level description compiler for designing of PLD/EPLD-based systems

Author

Deniziak, Stanislaw ; Sapiecha, Krzysztof

Author_Institution

Dept. of Comput. Sci., Kielce Univ. of Technol., Poland

Volume

1

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

201

Abstract

High-level synthesis of PLD/EPLD-based systems is considered. Behavioral description of the system is formulated using procedural CHDL called UPLAND. The description is verified by simulation and tests are generated assuming a typical variable stuck-at fault model. Then, UPLAND source description is automatically translated into its corresponding target input format of a low logic level designing tool where target PLD/EPLD devices are optional. Finally, a fast state encoding optimization procedure is applied so that the nearly minimal PLD/EPLD-based implementation of the input format is obtained

Keywords

circuit CAD; circuit layout CAD; circuit optimisation; high level synthesis; integrated circuit layout; programmable logic devices; CAD; CUPLAND; EPLD-based systems; PLD-based systems; UPLAND source description; behavioral level description compiler; fast state encoding optimization procedure; high-level synthesis; logic design; procedural CHDL; simulation; Circuit faults; Clocks; Computational modeling; Computer science; Control systems; Digital systems; Encoding; High level synthesis; Logic design; Logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.408790

Filename

408790