DocumentCode
292852
Title
FPGA-memory tradeoff in the high-level synthesis of FPGA-based reconfigurable systems
Author
Istiyanto, Jazi Eko ; Monaghan, Sean
Author_Institution
Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
Volume
1
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
209
Abstract
The paper presents problems of applying synthesis techniques to FPGA-based design. The target architecture consists of a linear array of FPGAs in which to each FPGA there is a RAM attached to it. An attempt to utilise RAM is illustrated with random number generator as an example
Keywords
circuit CAD; field programmable gate arrays; high level synthesis; programmable logic arrays; FPGA-based reconfigurable systems; FPGA-memory tradeoff; RAM; high-level synthesis; linear array; logic CAD; random number generator; Cost function; Digital systems; Field programmable gate arrays; Hardware; High level synthesis; Integrated circuit interconnections; Multiplexing; Polynomials; Random number generation; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408792
Filename
408792
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