The quantum capacitance limit of high-speed, low-power InSb nanowire field effect transistors

The performance metrics of InSb nanowire (NW) FETs are investigated using an analytical 2-band model and a seminumerical ballistic transport model. The first analysis of the diameter dependence of the current, gate delay, power-delay product, and energy-delay product of InSb NW FETs, which operate in the quantum capacitance limit (QCL), are presented. Because of their small density of states, relatively large diameter, les 60 nm, InSb NW FETs operate in the QCL. Both the energy-delay and power-delay products are reduced as the diameter is reduced, and optimum designs are obtained for diameters in the range of 10 - 40 nm. Power-delay product varies from 2times 10^-20 J to 68times 10^-20 J for all devices with a source Fermi level range of 0.1 - 0.2 eV. The gate delay time for all devices varies from 4 - 16 fs and decreases as the NW diameter increases. These NW FETs provide both ultra-low power switching and high-speed.