Title :
Estimating performance characteristics of loop transformations
Author :
Rim, Minjoong ; Jain, Rajiv
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fDate :
30 May-2 Jun 1994
Abstract :
In this paper we present estimation techniques for loop transformations. These estimation techniques can be used for design space exploration. They can be used to quickly evaluate the cost and performance characteristics of the transformations, thus helping the designer make the decision of applying the transformation or not. The estimates are verified for several transformations and are very close to the actual results
Keywords :
array signal processing; parallel algorithms; scheduling; systolic arrays; trees (mathematics); DSP algorithms; cost evaluation; design space exploration; loop folding; loop transformations; loop unrolling; performance characteristics; scheduling; systolic arrays; tree height reduction; Costs; Digital signal processing; Kernel; Space exploration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408802
