An analog MOS model for circuit simulation and benchmark test results

Author

Chang, Robert C H ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

1

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

311

Abstract

The BSIM plus MOS transistor model is developed for accurate and efficient analysis and simulation of submicron VLSI circuits. A compact parameter set is created to achieve high accuracy and continuity of the drain current and its derivatives in the subthreshold, triode and saturation regions of operation. Experimental results on individual transistors from deep submicron technologies are presented. Benchmark tests are performed to illustrate the salient features of the BSIM plus model

Keywords

MOS analogue integrated circuits; MOSFET; circuit CAD; circuit analysis computing; integrated circuit design; semiconductor device models; BSIM plus; MOS transistor model; analog MOS model; benchmark test results; circuit simulation; compact parameter set; drain current; saturation regions; submicron VLSI circuits; subthreshold regions; triode regions; Adders; Benchmark testing; CMOS logic circuits; Circuit simulation; Circuit testing; Delay; Intrusion detection; MOSFETs; Transconductance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.408817

Filename

408817