Iterated timing analysis with dynamic partitioning technique for bipolar transistor circuits

This paper presents relaxation-based algorithms with the dynamic partitioning technique for bipolar circuit analysis. In this technique, a circuit is partitioned dynamically based on the consideration of the operating region of specified bipolar devices throughout the simulation interval. This technique has been used already in the waveform relaxation method, and, in this paper, is implemented in the Iterated Timing Analysis (ITA). The present method is applied to the transient simulation of several digital bipolar junction transistor (BJT) circuits and compared with the waveform relaxation method