Scaling of 32nm low power SRAM with high-K metal gate

Author

Yang, H.S. ; Wong, R. ; Hasum, R. ; Gao, Y. ; Kim, N.S. ; Lee, D.H. ; Badrudduza, S. ; Nair, Dhruv ; Ostermayr, M. ; Kang, H. ; Zhuang, H. ; Li, J. ; Kang, L. ; Chen, X. ; Thean, A. ; Arnaud, F. ; Zhuang, L. ; Schiller, C. ; Sun, D.P. ; Teh, Y.W. ; Wallne

Author_Institution

Semicond. Res. & Dev. Center (SRDC), IBM Microelectron., Hopewell Junction, NY

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum² and 0.124 mum². SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T_inv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum² cell to meet low power application requirements.

Keywords

SRAM chips; silicon compounds; dual-ground write; high-k metal gate; low power SRAM; mismatch reduction; size 32 nm; ultra dense cell process; Dielectric devices; Fluctuations; Gate leakage; High K dielectric materials; High-K gate dielectrics; Microelectronics; Random access memory; Research and development; Stability; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796660

Filename

4796660