A new VLSI architecture for large kernel real time convolution

A VLSI architecture is introduced to achieve a single-chip real-time implementation of large-kernel convolutions. The architecture provides a way to organize the computation in order to lower the I/O bandwidth to 2 pixels per clock cycle, without increasing the internal storage. As a result, the whole silicon array can be dedicated to computation, without excessive external memory requirements, opening the way to single-chip, very-large-kernel convolutions. As an example, a 16×16 convolution or correlation architecture has been devised based on a 1.2-μm CMOS process. The same architecture can be used for data processing involving 2-D data convergence