Title :
A simultaneous placement and global routing algorithm for FPGAs
Author :
Togawa, Nozomu ; Sato, Masao ; Ohtsuki, Tatsuo
Author_Institution :
Dept. of Electron. & Commun. Eng., Waseda Univ., Tokyo, Japan
fDate :
30 May-2 Jun 1994
Abstract :
An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness
Keywords :
circuit layout CAD; field programmable gate arrays; integrated circuit layout; logic CAD; logic partitioning; network routing; programmable logic arrays; FPGA layout algorithm; simultaneous placement/global routing algorithm; top-down hierarchical bi-partitioning; Circuits; Field programmable gate arrays; Functional programming; Logic functions; Logic programming; Routing; Switches; Terminology;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408843
