DocumentCode
2929056
Title
Improved effective switching current (IEFF +) and capacitance methodology for CMOS circuit performance prediction and model-to-hardware correlation
Author
Yu, Xiaojun ; Han, Shu-Jen ; Zamdmer, Noah ; Deng, Jie ; Nowak, Edward J. ; Rim, Ken
Author_Institution
Semicond. Res. & Dev. Center, IBM, Hopewell Junction, NY
fYear
2008
fDate
15-17 Dec. 2008
Firstpage
1
Lastpage
4
Abstract
New effective drive current IEFF + methodologies are demonstrated in this paper to address predictability of circuit performance across wide Vt range and accuracy of effective resistance REFF prediction-to-hardware correlation. Two separate IEFF definitions are adopted for delay performance prediction (IEFF = [IH + IL]/2), and ring AC/DC prediction-tohardware correlation analysis (IEFF + = [1.15IH + IL + GDS,LIN* VDD/80]/2). IEFF + results in perfect matching in ring AC and DC effective resistance across SOI and bulk technologies. IEFF combined with Vt-dependent effective switching capacitance (CEFF_Delay) also leads to good match between predicted performance and spice simulation across wide Vt range using simple CMOS device parameters.
Keywords
CMOS integrated circuits; SPICE; integrated circuit modelling; integrated circuit reliability; silicon-on-insulator; switching; CMOS circuit performance prediction; SOI technology; SPICE simulation; bulk technology; capacitance methodology; delay performance prediction; effective switching current; model-to-hardware correlation; ring AC/DC prediction-to-hardware correlation; Analytical models; Capacitance; Circuit optimization; Circuit simulation; Delay effects; Inverters; Performance analysis; Predictive models; Semiconductor device modeling; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location
San Francisco, CA
ISSN
8164-2284
Print_ISBN
978-1-4244-2377-4
Electronic_ISBN
8164-2284
Type
conf
DOI
10.1109/IEDM.2008.4796666
Filename
4796666
Link To Document