A two stage structure for high order multi-bit Σ-Δ ADC with multiplier-less digital correction logic

This paper presents the design methodology of Σ-Δ ADC that uses a high order single bit first stage, and a multi bit first order second stage and introduces a novel multiplier-less high order digital correction block. The selection of the number of bits and order is done by design graphs that are obtained through numerous simulations under practical tolerances in implementation parameters. By using an example of a 3rd order first stage with a 5-bit second stage, we show that the over-sampling ratio can be reduced to (=<32) while achieving a high bit resolution (>16 bits) for 2% mismatch implementation tolerances between analog and digital parts. Our approach results in an overall increase in the maximum baseband frequency, while the additional digital correction logic is minimal