Title :
Guard Ring Interactions and their Effect on CMOS Latchup Resilience
Author :
Farbiz, Farzan ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL
Abstract :
Latchup resilience is studied by considering interactions between multiple carrier collectors and N or P-type guard rings. It is shown that P-type taps and guard rings have a deleterious effect on latchup triggered by minority carriers. Physical explanations are provided based on measurements in 90 and 130 nm technologies as well as extensive device simulations.
Keywords :
CMOS integrated circuits; CMOS latchup resilience; deleterious effect; guard ring interactions; multiple carrier collectors; size 130 nm; size 90 nm; CMOS technology; Circuit simulation; Circuit testing; Diodes; Electrons; Electrostatic discharge; MOS devices; Protection; Resilience; Voltage;
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
DOI :
10.1109/IEDM.2008.4796690
