Title :
Session 16: Process technology - Ge-Channel CMOS and advanced gate stacks
Author_Institution :
Intel, Kentaro Shibahara, Hiroshima University, Japan
Abstract :
The first paper describes Ge-Channel MOSFETs with S/D formed by metal-induced dopant activation. The second paper describes interface engineering and characterization of Hi-K in Ge MOSFET with 1nm EOT. The third paper relates to fabrication of ultra-thin GeOI MOSFETs. The fourth paper describes InGaAs MOSFETs with in-situ PH3 surface plasma passivated HfAlO/TaN and HfO2/TaN gate stacks. The fifth paper in this session describes Fluorinated HfO2 gate stacks for CMOS for improved reliability. The last paper relates to control of threshold voltage variability in Hi-k-metal Gate stacks through control of grain size and crystallinity in metal gates.
Keywords :
CMOS process; CMOS technology; Fabrication; Grain size; Hafnium oxide; Indium gallium arsenide; MOSFETs; Plasmas; Size control; Voltage control;
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
DOI :
10.1109/IEDM.2008.4796701
