Title :
Exploiting FPGA block memories for protected cryptographic implementations
Author :
Bhasin, Shubhendu ; Wei He ; Guilley, Sylvain ; Danger, Jean-Luc
Author_Institution :
Inst. Mines-Telecom, Telecom-ParisTech, Paris, France
Abstract :
Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security.
Keywords :
application specific integrated circuits; coprocessors; cryptography; field programmable gate arrays; integrated memory circuits; logic design; logic testing; AES-128 coprocessor; ASIC; BRAM; DSP; FPGA block memories; Xilinx Virtex-5 chips; digital signal processing cores; dual-rail logic; dual-rail precharge logic countermeasure; embedded CPU; field programmable gate arrays; huge block memory; intrinsic countermeasures; masking; physical attacks; protected cryptographic implementations; Cryptography; Field programmable gate arrays; Logic gates; Registers; Resistance; Routing; Block Memories; Countermeasures; FPGA; Side-Channel Analysis;
Conference_Titel :
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on
Conference_Location :
Darmstadt
Print_ISBN :
978-1-4673-6180-4
DOI :
10.1109/ReCoSoC.2013.6581529