Title :
A formal approach to pipeline optimization in synthesis of digital signal processors with fine grain parallelism
Author :
Zimmermann, S. ; Lueder, E.
Author_Institution :
Inst. fur Netzwerk- und Systemtheor., Stuttgart Univ., Germany
fDate :
30 May-2 Jun 1994
Abstract :
In this paper we present a constraint-model for pipelined digital signal processors, based on mathematical programming. Our intention is to maximize the utilization of allocated hardware components by minimizing the clock-cycle time and the period of cyclic innermost loop schedules in one approach. The constraint formulations are developed for a very general multiphase clocking environment with an FPGA (Field Programmable Gate Array) target architecture
Keywords :
Clocks; Delay; Digital signal processors; Field programmable gate arrays; Hardware; Mercury (metals); Parallel processing; Pipeline processing; Signal processing algorithms; Signal synthesis;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408970
