Taking the next step in moore´s law: Designs turn to enable next technology node

Moore´s Law is an expression of the path that semiconductor vendors have taken to achieve competitive advantage relative to their peers and their past. A new class of challenges threatens the ability of logic vendors to gain competitive advantage by migrating to 45 nm, 32 nm, and below. Achieving the required time to market with economically acceptable yield levels and maintaining them in volume production has become a daunting task in the most advanced technology nodes. One of the primary reasons is the relative increase in process variability in each generation. In the older technology generations, manufacturing yield loss was dominated by random defects. This situation started to change rapidly at the 130 nm technology node in which product layout systematic effects became more critical. More recently, due to challenging product performance requirements and increased process variability, parametric yield losses have become significant as well.