DocumentCode :
2930069
Title :
More strain and less stress- the guideline for developing high-end strained CMOS technologies with acceptable reliability
Author :
Chung, Steve S. ; Hsieh, E.R. ; Huang, D.C. ; Lai, C.S. ; Tsai, C.H. ; Liu, P.W. ; Lin, Y.H. ; Tsai, C.T. ; Ma, G.H. ; Chien, S.C. ; Sun, S.W.
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
fYear :
2008
fDate :
15-17 Dec. 2008
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65 nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; integrated circuit design; integrated circuit reliability; silicon-on-insulator; CMOS device reliability; DCIV method; SiC; SiGe; charge pumping; high-end strained CMOS technology; hot-carrier immunity; integrated circuit design; interface quality; interface trap profiling; nMOSFET; negative bias temperature instability; off-state junction leakage; silicon-on-insulator; size 65 nm; CMOS technology; Capacitive sensors; Charge measurement; Charge pumps; Current measurement; Guidelines; Hot carriers; MOSFETs; Reliability engineering; Silicon carbide;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
8164-2284
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
Type :
conf
DOI :
10.1109/IEDM.2008.4796718
Filename :
4796718
Link To Document :
بازگشت