DocumentCode :
2930081
Title :
Trimming of IC timing and delay by backside FIB processing - comparison of conventional and strained technologies
Author :
Schlangen, Rudolf ; Leihkauf, Rainer ; Lundquist, Ted ; Egger, Peter ; Kerst, Uwe ; Boit, Christian
Author_Institution :
Berlin Univ. of Technol., Berlin
fYear :
2008
fDate :
15-17 Dec. 2008
Firstpage :
1
Lastpage :
4
Abstract :
Rapid prototyping options provided by backside FIB preparation are expanded by trimming device delay to the desired quantity. Using inverter chains in 180 nm standard CMOS technology, proper FIB backside treatment is demonstrated to speed up or slow down devices by more than 20%. This result agrees well with device simulations and applies in principle to any technology. Devices from a 65 nm strained CMOS process show an even increased effect, further expanding the trimming potential of backside FIB.
Keywords :
CMOS integrated circuits; MOSFET; delays; focused ion beam technology; nanoelectronics; FIB processing delay comparison; IC time trimming; backside FIB preparation; focused ion beam technology; prototyping option; size 180 nm; size 65 nm; standard CMOS technology; strained CMOS process; trimming device simulation; CMOS process; CMOS technology; Circuit simulation; Delay; Integrated circuit interconnections; Inverters; Packaging; Prototypes; Technological innovation; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
8164-2284
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
Type :
conf
DOI :
10.1109/IEDM.2008.4796719
Filename :
4796719
Link To Document :
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