A design technique for polyphase decimators with binary constrained coefficients for high resolution A/D converters

This paper presents a design technique for high fidelity multistage decimation filters based on polyphase and decimator structures, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 15 bit resolution. The resulting filter coefficients are constrained to the required bit length using a “bit flipping algorithm”. This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to other approximation methods. The coefficients and frequency responses of the cascaded filter are reported