Title :
Protecting caches against multi-bit errors using embedded erasure coding
Author :
BanaiyanMofrad, Abbas ; Ebrahimi, Mojtaba ; Oboril, Fabian ; Tahoori, Mehdi B. ; Dutt, Nikil
Author_Institution :
Univ. of California, Irvine, Irvine, CA, USA
Abstract :
Technology scaling advancement coupled with operational and environmental effects make embedded memories more vulnerable to both manufacturing and transient errors including multi-bit upsets. Conventional error correcting codes incur high latency, area, and power overheads to correct multi-bit errors. In this paper, we propose Embedded Erasure Coding (EEC), a low-cost technique that can correct multi-bit errors with low overheads. This technique employs interleaved parity bits to provide a fast and low-cost multi-bit error detection. Using the erasure coding concept, the error correction is done by reconstructing the contents of the erroneous cache blocks within each cache set. Our proposed technique trades the performance for higher reliability by reserving a part of the cache (e.g. one way) to store the erasure codes. Our simulation results show that EEC provides high reliability (100% error detection and correction) with lower area overhead as compared to other state-of-the-art techniques while imposing negligible performance overhead (3%).
Keywords :
cache storage; error correction codes; interleaved codes; cache blocks; embedded erasure coding; embedded memories; error correcting codes; interleaved parity bits; multi-bit errors; Complexity theory; Decoding; Encoding; Error correction codes; Program processors; Random access memory; Reliability;
Conference_Titel :
Test Symposium (ETS), 2015 20th IEEE European
Conference_Location :
Cluj-Napoca
DOI :
10.1109/ETS.2015.7138735