A fully-digital, 2-MB/sec, CMOS data separator

Author

Saban, Rami ; Efendovich, Avner

Author_Institution

Nat. Semicond. Corp., Herzlia, Israel

Volume

3

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

53

Abstract

Our innovative design for a data separator utilizes digital logic only and is implemented in standard CMOS technology. Therefore, it can easily be adapted to different processes, voltage supplies, layouts, scales, etc. The Digital Data Separator (DDS) presented in this paper can work with either a 5 V or a 3 V power supply and with widely fluctuating process parameters. This DDS supports data rates of 250 KB/sec, 300 KB/sec, 500 KB/sec, 1 MB/sec and 2 MB/sec. With all data rates, it achieves window margins above 60%, within the range of ±8% MSV and ±3% ISV @ 1 kHz. We used a unique frequency multiplier that utilizes a Digitally Controlled Oscillator (DCO) in order to provide high resolution to achieve a large window margin

Keywords

CMOS digital integrated circuits; data communication equipment; digital phase locked loops; frequency multipliers; synchronisation; timing; 250 KB/s to 2 MB/s; 3 V; 5 V; CMOS data separator; digital logic; digitally controlled oscillator; frequency multiplier; standard CMOS technology; CMOS technology; Clocks; Communication system control; Data mining; Digital control; Frequency conversion; Particle separators; Power supplies; Signal resolution; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409100

Filename

409100