Fault-tolerant architectures for shared buffer memory switch

The Shared Buffer Memory Switch (SBMS) is one of the most attractive alternatives for the ATM switch design for future B-ISDN telecommunications. In an SBMS, cells destined for different output ports are stored in one shared buffer and organized as single-link lists. However, for some unexpected faults in address chain memory, catastrophic damage will result in the SBMS to read out the cells not belonging to the original port. More seriously, the cells incoming to the faulty port will never be read out from the shared memory, thus exhausting the available memory space eventually. In this paper, we survey fault tolerant methods to combat address chain faults in SBMS. Specifically, we propose a double-link list based SBMS architecture which is robust if the address chain memory has less than two faults for each port