Design of a 6-bit 5.4-Gsamples/s CMOS D/A converter for DS-CDMA UWB transceivers

This paper presents a design of a 6-bit 5.4-Gsamples/s D/A converter in IBM 0.13 μm CMOS technology for DS-CDMA UWB transceivers. The high conversion rate and low supply voltage of 1.5 V make the design a challenge. To reduce the time constant of the circuit, we propose a two-stage current-steering topology, in which the distribution of the resistive and capacitive loads is balanced at the two stages. We also propose a folded-cascode current source cell that eliminates the need to control the crossing-points of the switch signals and minimizes the digital feedthrough. The current source cell does this without sacrificing headroom, so the circuit is suitable for a low supply voltage. Post-layout simulation has been performed to estimate performance. At the conversion rate of 5.4 Gsamples/s, the spurious free dynamic range (SFDR) is greater than 38 dB for three different signal frequencies. Both the integral nonlinearity (INL) and differential nonlinearity (DNL) stay within 0.3 LSB. The layout occupies a small active area of 110 μm × 90 μm, and the D/A converter consumes only 20 mW of power.