Comprehensive performance assessment of scaled (110) CMOSFETs based on understanding of STI stress effects and velocity saturation

Author

Saitoh, Masumi ; Yasutake, Nobuaki ; Nakabayashi, Yukio ; Numata, Toshinori ; Uchida, Ken

Author_Institution

Corp. R&D Center, Adv. LSI Technol. Lab., Toshiba Corp., Kawasaki

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

We present the systematic study on dominant factors of the performance of scaled (110) n/pFETs. STI stress effects and velocity saturation phenomena in narrow and short (110) devices are investigated for the first time. I_dsat of scaled (110) nFETs approaches (100) nFETs as a result of mu increase due to transverse compressive stress from STI in (110) nFETs and strong velocity saturation in (100) nFETs. Meanwhile, I_dsat of scaled (110) pFETs are still superior to (100) pFETs due to high mu of (110) pFETs and weaker velocity saturation than nFETs as long as R_sd of (110) pFETs is well suppressed. As a result, scaled (110) CMOS shows excellent performance even without intentional stressors.

Keywords

CMOS integrated circuits; MOSFET; isolation technology; silicon; CMOSFET; STI stress effects; Si (110); shallow trench isolation; velocity saturation; CMOS technology; CMOSFETs; Capacitive sensors; Compressive stress; Degradation; FETs; Laboratories; Large scale integration; MOSFETs; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796754

Filename

4796754