Session 26: Process technology - interconnect and 3D-IC technologies

This session contains seven papers describing advances in Cu/Low-k interconnect and 3D-IC technology. The first three papers concern 3D-IC technologies. Sillon et al., from CEA-LETI describe three advances in 3D integration. Liu et al., from IBM describe a fine pitch (5 um) and high aspect ratio (17:1) tungsten through-wafer via technology enabling 3D stacking. Through silicon vias are inserted between metal-1 and contact for ring oscillators on different tiers by Olman et al., from IMEC. The fourth paper, by Chai from Hong Kong University of Science and Technology presents copper and carbon nanotube composites for improving electromigration lifetime. The last three papers of the session discuss advantage in Cu/low-k interconnect. Kawahara et al., from NEC Electronics discusses Cu/Low-k dual damascene contacts to enhance RF performance in 40 nm CMOS devices. Oda et al., from Selete utilizes silylated porous silica (k=2.1) in ultra low-k/Cu dual damascene integration. A high performance copper interconnection scheme using a molecular pore stack containing SiCOH to reduce the process-induced damage is presented by Ueki et al., from NEC Electrics.