Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs

This paper presents an overview of current 3D technologies development at CEA/LETI Minatec. Three different 3D approaches are described, and can be seen as 3 generations for that emerging field. An original through silicon via (TSV) process for CMOS image sensors (CIS) is presented, and electrical results showing very low resistances and high yields are described. A similar TSV process, combined with temporary bonding and low pitch interconnects is used to address the second generation of 3D integration, the active silicon interposer. A first demonstrator of a TSV process on thin wafer is described. Some reliability results on an innovative technology for flip chip, fully compatible with chip stacking, are detailed. It will also be shown that by developing advanced technology like direct bonding and high density TSV, CEA-Leti is also preparing ultimate 3D integration, with very high density interconnects.