Aging guardband reduction through selective flip-flop optimization

Bias Temperature Instability (BTI) affects both timing and functionality of Flip-Flops (FFs). In a typical processor, a considerable portion of FFs always operate under severe BTI stress independent of the running workload. This leads to a serious timing degradation in these FFs, and to avoid timing violations in field, they mandate a large aging guardband (timing margin). In this paper, we propose a method to mitigate the BTI-induced aging of such FFs via transistor sizing optimization. The optimized FFs are more resilient against BTI stress compared to the original ones. The imposed overall leakage is negligible, and the area of the optimized FFs is similar to the original ones in order to facilitate the replacement of the original FFs with optimized alternatives in the circuit layout. Simulation results show that incorporating the optimized FFs in a processor can reduce the timing guardband of the processor by 22.8% compared to the original design, which translates into prolonged lifetime and more reliability.