Title :
RF performance boosting for 40nm-node CMOS device by low-k/Cu dual damascene contact
Author :
Kawahara, J. ; Hijioka, K. ; Kume, I. ; Nagase, H. ; Tanabe, A. ; Ueki, M. ; Yamamoto, H. ; Ito, F. ; Inoue, N. ; Tagami, M. ; Furutake, N. ; Onodera, T. ; Saito, S. ; Takeuchi, T. ; Fukai, T. ; Asada, M. ; Arita, K. ; Motoyama, K. ; Nakajima, A. ; Nakaza
Author_Institution :
LSI Fundamental Res. Lab., NEC Electron. Corp., Sagamihara
Abstract :
To enhance RF performance, low-k/Cu dual-damascene (DD) contact is implemented into 40 nm-node CMOS devices for the first time. The Cu DD contact in reliable double-layered low-k films of silica-carbon composite (SCC, k=3.1) and SiOCH (k=3.1) boosts the cut-off frequency (fT) and the maximum oscillation frequency (fmax) by 8.0 % and 10.5% referred to those of the conventional SiO2/W-plug structure, respectively. The low-k/Cu-DD contact structure becomes effective to reduce the parasitic factors in the scaled-down 40 nm-node more than the 55 nm-node reported. The contact resistance and the parasitic capacitance (Cgs) are reduced by 80% (one-fifth) and 17% referred to those of the conventional SiO2/W-plug structure, respectively. The low-k/Cu DD contact is essential to scaled-down CMOS devices for RF/ubiquitous applications.
Keywords :
CMOS integrated circuits; contact resistance; copper; low-k dielectric thin films; silicon compounds; CMOS device; double-layered low-k films; low-k/copper dual damascene contact; oscillation frequency; parasitic factors; silica-carbon composite; size 40 nm; Boosting; CMOS process; CMOS technology; Contact resistance; Cutoff frequency; Etching; MOSFETs; Parasitic capacitance; RF signals; Radio frequency;
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
DOI :
10.1109/IEDM.2008.4796765
