Comprehensive study of 32 nm node ultralow-k/Cu (keff=2.6) dual damascene integration featuring short TAT silylated porous silica (k=2.1)

Author

Oda, N. ; Chikaki, S. ; Kubota, T. ; Nakao, S. ; Tomioka, K. ; Soda, E. ; Nakamura, N. ; Nogawa, J. ; Kawashima, Y. ; Hayashi, R. ; Saito, S.

Author_Institution

Semicond. Leading Edge Technol., Inc., Tsukuba

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

A comprehensive study of low-k/Cu integration featuring short TAT (turnaround time) silylated scalable porous silica (Po-SiO, k=2.1) with high porosity (50%) is presented. The TAT for silylation is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, 140 nm pitch dual damascene structure is successfully achieved. The wiring capacitance showed 10% reduction compared with the conventional porous SiOC (ULK, k=2.65). Sufficient interconnect reliability and packaging characteristics for circuit-under-pad structure are also obtained. The predicted circuit-performance was 8% higher than ULK in 32 nm node.

Keywords

integrated circuit interconnections; integrated circuit reliability; packaging; permittivity; porosity; porous materials; silicon compounds; dual damascene structure; interconnect reliability; low-k/Cu integration; packaging; porosity; porous silica; silylation; size 32 nm; turnaround time; wiring capacitance; Air gaps; Capacitance; Circuit testing; Damascene integration; Integrated circuit interconnections; Lead compounds; Lithography; Packaging; Silicon compounds; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796766

Filename

4796766