High performance Cu interconnects with damage-less full molecular-pore-stack (MPS) SiOCH for 32nm-node LSIs and beyond

Damage-less full molecular-pore-stack SiOCH (MPS) / Cu interconnect is developed to reduce effective k-value (k_eff). MPS with high endurance against plasma processes is introduced into both via and trench dielectrics without hard mask (HM). Low friction slurry and chemical modification of MPS surface by He-plasma treatment suppress defect generation during direct CMP of the MPS surface. The full-MPS interconnect with low-k (k=3.1) cap demonstrates 10% lower inter-line capacitance and 34% lower inter-layer capacitance than the full-SiOCH (k=3.0) interconnect with SiCN-cap (k=4.9). The effective k-value k_eff reduces to 2.67 for the damage-less full MPS structure which is applicable to 32 nm LSIs and beyond.