Title :
Asynchronous implementation of the add compare select processor for communication systems
Author :
Eshraghi, Aria ; Fiez, Terri ; Fischer, Tom
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
fDate :
30 May-2 Jun 1994
Abstract :
This paper presents an asynchronous version of the Add-Compare-Select (ACS) processor. It is shown that in a statistical sense the asynchronous version of the ACS processor is faster than the synchronized version. Thus, it provides an alternative solution to overcome the speed bottleneck of the ACS processor for the Viterbi processor. An 8-bit asynchronous ACS processor requires 1.2 mm×1.2 mm in a 2μ CMOS technology
Keywords :
CMOS logic circuits; Viterbi decoding; adders; asynchronous circuits; comparators (circuits); 2 micron; 8 bit; ACS processor; CMOS technology; Viterbi processor; add compare select processor; adders; asynchronous implementation; comparators; speed bottleneck; CMOS process; CMOS technology; Computer science; Convolutional codes; Data compression; Decoding; Digital communication; Equations; Logic; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409156
