Author :
Diaz, C.H. ; Goto, K. ; Huang, H.T. ; Yasuda, Yuri ; Tsao, C.P. ; Chu, T.T. ; Lu, W.T. ; Chang, Vincent ; Hou, Y.T. ; Chao, Y.S. ; Hsu, P.F. ; Chen, C.L. ; Lin, K.C. ; Ng, J.A. ; Yang, W.C. ; Chen, C.H. ; Peng, Y.H. ; Chen, Chaoteng Jordan ; Chen, C.C. ;
Abstract :
A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at Ioff=100 nA/mum, Vdd=1 V, 30 nm physical gate length and 130 nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 muA/mum (n/p) at total Ioff ~1 nA/mum @ Vdd = 1V. Low sub-threshold leakage was achieved while successfully containing Iboff and Igoff well below 1 nA/um. Ultra high density 0.15 um2 SRAM cell is fabricated by high NA 193 nm immersion lithography. Functional 2 Mb SRAM test-chip in 32 nm design rule has been demonstrated with a controllable manufacturing window.
Keywords :
SRAM chips; high-k dielectric thin films; immersion lithography; metal-insulator boundaries; SRAM cell; drive currents; gate-first high-k/metal-gate technology; high-performance low-power applications; immersion lithography; low sub-threshold leakage; size 30 nm; size 32 nm; CMOS technology; Chaos; Dielectric substrates; Gate leakage; High K dielectric materials; High-K gate dielectrics; Lithography; Random access memory; Semiconductor device manufacture; Testing;
