Author :
Arnaud, F. ; Liu, J. ; Lee, Y.M. ; Lim, K.Y. ; Kohler, S. ; Chen, J. ; Moon, B.K. ; Lai, C.W. ; Lipinski, M. ; Sang, L. ; Guarin, F. ; Hobbs, C. ; Ferreira, P. ; Ohuchi, K. ; Li, J. ; Zhuang, H. ; Mora, P. ; Zhang, Q. ; Nair, D.R. ; Lee, D.H. ; Chan, K.K.
Author_Institution :
STMicroelectronics, IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY
Abstract :
This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um2 SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.
Keywords :
1/f noise; CMOS digital integrated circuits; integrated circuit noise; integrated circuit reliability; low-power electronics; 1/f noise; BEOL scheme; CMOS technology; RC delay; SRAM cell; bias temperature instability; extreme low k dielectric; gate dielectric breakdown; hierarchical back-end-of-line scheme; high speed digital transistors; high-k dielectric; hot carrier injection; low power applications; matching factor improvement; reliability; ring oscillator; size 32 nm; static noise margin; temperature 125 degC; CMOS technology; Delay; High K dielectric materials; High-K gate dielectrics; Hot carrier injection; Human computer interaction; Low voltage; Random access memory; Ring oscillators; Wiring;
