BiCMOS active-pull-down non-threshold logic circuits for high-speed low-power applications

Author

Sharaf, K.M. ; Elmasry, M.I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

4

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

19

Abstract

A new active-pull-down non-threshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an APD-NMOS emitter-follower stage. Simulation results based on 0.6-μm BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4× improvement in the load driving capability and 3.4× improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV. A comparison of critical-path delay has showed the superiority of the novel circuit over ECL circuits especially in the low-power region

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; NOR circuits; delays; logic design; logic gates; 0.6 micron; BiCMOS circuit; NMOS emitter-follower stage; active-pull-down type; high-speed IC; low-power applications; nonthreshold logic circuits; Application software; BiCMOS integrated circuits; Circuit simulation; Delay; Energy consumption; Logic circuits; Logic gates; MOS devices; Power dissipation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409186

Filename

409186