Author :
Watanabe, R. ; Oishi, A. ; Sanuki, T. ; Kimijima, H. ; Okamoto, K. ; Fujita, S. ; Fukui, H. ; Yoshida, K. ; Otani, H. ; Morifuji, E. ; Kojima, K. ; Inohara, M. ; Igrashi, H. ; Honda, K. ; Yoshimura, H. ; Nakayama, T. ; Miyake, S. ; Hirai, T. ; Iwamoto, T.
Abstract :
Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin is also accomplished by minimizing random impurity fluctuation using Hf doped silicate as gate dielectrics. In addition, novel DFM (Design for Manufacturing) techniques are introduced for systematic yield improvement.
Keywords :
CMOS integrated circuits; SRAM chips; design for manufacture; integrated circuit yield; low-power electronics; system-on-chip; CMOS technology; SRAM chips; design for manufacturing; gate density; power reduction; static noise margin; system-on-chip; systematic yield improvement; CMOS logic circuits; CMOS technology; Dielectrics; Fluctuations; Hafnium; Impurities; Logic devices; Low voltage; Radio frequency; Random access memory;
