A power-saving technique for bit-serial DSP ASICs

The bit-serial processing technique arises to be a competitor of the traditional bit-parallel processing technique to implement DSP ASICs, because the bit-serial implementation of DSP ASICs usually results in small communication cost and compact processing elements. However, shift registers are usually used to realize delays required by the DSP algorithms. Long shift registers consume a lot of power for they are clocked at very high frequency. More troublesome is that the power associated with driving a lot of clocked transistors has to be supplied by the clock lines (not power supply lines), which may cause clock distribution problem. In this paper, we propose a power-saving technique without speed penalty by getting rid of unnecessary data shifting and long shift registers. All the delay elements in the traditional long shift registers are realized by DRAM-alike memory cells and data is not shifted but accessed by using shared cyclical address decoders. The measurement of a test chip indicates a power saving by 4 times when we need to use 15 16-bit shift registers. More power saving is expected when we need more shift registers for large DSP ASICs