Title :
Design of novel serial-parallel inner-product processors
Author :
Fahmi, Maher N. ; El-Guibaly, Fayez ; Sunder, Sreenivasachar ; Shpak, Dale J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
fDate :
30 May-2 Jun 1994
Abstract :
A novel, high performance serial-parallel fixed-point inner-product processor is derived using the dependence graph mapping technique. The proposed scheme is AT2 efficient, offers a highly regular structure, and is ideally suited for applications requiring small processor area, large word lengths, while maintaining high speed and double precision processing. Thus, the design is well suited for VLSI and FPGA implementations. A comparison in terms of speed and area between our scheme and conventional inner-product processors is presented. The proposed hardware structure simultaneously achieves a significant time and area savings
Keywords :
VLSI; digital arithmetic; digital signal processing chips; field programmable gate arrays; integrated circuit design; iterative methods; multiplying circuits; FPGA; VLSI; area saving; dependence graph mapping technique; double precision processing; fixed-point inner-product processor; highly regular structure; processor area; serial-parallel inner-product processors; word lengths; Delay; Design engineering; Educational institutions; Field programmable gate arrays; High performance computing; Iterative algorithms; Military computing; Process design; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409195
