Title :
Pseudo-random vector compaction for sequential testability
Author :
BenHamida, Naim ; Kaminska, Bozena ; Savaria, Yvon
Author_Institution :
Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
fDate :
30 May-2 Jun 1994
Abstract :
In this paper, a pseudo-random vector compaction technique for sequential circuits is presented. This technique is based on sequential testability measures and the iterative model. The optimum number of circuit duplications is deduced from the testability analysis. The pseudo random vector compaction consists of conserving the vectors that detect faults and the n-1 previous vectors, where n is the optimum number of circuit duplications. The results indicate that fault coverage produced by 200000 pseudo-random vectors is exactly reproduced by a small set of vectors which do not exceed 1000 vectors for almost all the benchmark circuits
Keywords :
automatic testing; fault diagnosis; integrated circuit testing; iterative methods; logic testing; sequential circuits; ATPG; benchmark circuits; circuit duplications; fault coverage; iterative model; pseudo-random vector compaction; sequential circuits; sequential testability; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Compaction; Electrical fault detection; Fault detection; Performance evaluation; Sequential analysis; Sequential circuits;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409197
