Author :
Hasegawa, S. ; Kitamura, Y. ; Takahata, K. ; Okamoto, H. ; Hirai, T. ; Miyashita, K. ; Ishida, T. ; Aizawa, H. ; Aota, S. ; Azuma, A. ; Fukushima, T. ; Harakawa, H. ; Hasegawa, E. ; Inohara, M. ; Inumiya, S. ; Ishizuka, T. ; Iwamoto, T. ; Kariya, N. ; Koj
Abstract :
For the first time, we demonstrate standard cell gate density of 3650 KGate/mm2 and SRAM cell of 0.124 mum2 for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45 nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP) and poly/SiON gate stack.
Keywords :
CMOS integrated circuits; SRAM chips; high-k dielectric thin films; lithography; CMOS platform technology; SRAM cell; advanced single exposure lithography; gate-first metal gate-high-k process; size 32 nm; standard cell gate density; CMOS logic circuits; CMOS process; CMOS technology; Cost function; Degradation; High K dielectric materials; High-K gate dielectrics; Lithography; Manufacturing processes; Random access memory;
