Analog implementation of class-IV partial-response Viterbi detector

Viterbi detectors have traditionally been realized in digital hardware and/or software. However, analog implementations can lead to smaller, faster and lower power-consumption circuits. In this paper, a new architecture for realizing a class-IV partial-response Viterbi detector is proposed and implemented using simple analog building blocks. This architecture is more robust against offsets and gain errors than other analog detectors and should operate faster when implemented in the same technology. In addition, it is shown that the Viterbi detector is an adaptive-threshold device with a complexity much less than that of a typical 6-bit A/D convertor required in digital realizations. Performance of the detector is evaluated by simulations and experimental results