DocumentCode :
293143
Title :
High sample rate architectures for block adaptive filters
Author :
Karkada, Srikanth ; Chakrabarti, Chaitali ; Spanias, Andreas
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Volume :
4
fYear :
1994
fDate :
30 May-2 Jun 1994
Firstpage :
131
Abstract :
In this paper we propose a variety of architectures for implementing block adaptive filters in the time-domain. These filters are based on a block implementation of the least mean squares (BLMS) algorithm. First, we present an architecture which directly maps the BLMS algorithm into an array of processors. Next, we describe an architecture where the weight vector is updated without explicitly computing the filter error. Third, we describe an architecture which exploits the redundant computations of overlapping windows. All the architectures have a significantly smaller sample period compared to frequency domain implementations. Moreover, the sample periods can be reduced even further by applying relaxed look-ahead techniques
Keywords :
adaptive filters; digital filters; least mean squares methods; pipeline processing; block LMS algorithm; block adaptive filters; high sample rate architectures; least mean squares algorithm; look-ahead techniques; sample periods; time-domain implementation; weight vector updating; Adaptive filters; Computer architecture; Delay; Digital filters; Error correction; Finite impulse response filter; Frequency domain analysis; Least squares approximation; Pipeline processing; Time domain analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
Type :
conf
DOI :
10.1109/ISCAS.1994.409214
Filename :
409214
Link To Document :
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