High performance CMOS macromodule layout synthesis

Author

Kim, Jaewon ; Kang, S.M. ; Sapatnekar, Sachin S.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

Volume

4

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

179

Abstract

A new high-performance CMOS macromodule layout synthesis system is presented. The layout is based on a new flexible logic cell array platform and channelless routing with compaction, utilizing three layers of metallic interconnects. The flexible cells are placed into rows whose heights can be customized to minimize the total area, while meeting the user-specified aspect ratio of the macromodule. The triple metal layer channelless routing problem with irregular boundaries is mapped to the composite problem of channelless two-layer routing and segment squeezing with layer conversion. To meet the user-specified specifications on circuit delays, in addition to well-established placement and routing, a rigorous transistor sizing program, which employs convex programming techniques, is used to find the minimum active area that satisfies all the delay specifications. The optimal transistor sizes are then implemented in the flexible cell and a new layout is generated. This process is iterated until the layout meets all the timing requirements

Keywords

CMOS logic circuits; circuit layout CAD; convex programming; delays; integrated circuit design; integrated circuit interconnections; logic CAD; logic arrays; network routing; timing; CMOS macromodule; channelless routing; circuit delays; compaction; convex programming techniques; delay specifications; flexible logic cell array platform; irregular boundaries; layout synthesis system; metallic interconnects; minimum active area; segment squeezing; timing requirements; transistor sizing; user-specified aspect ratio; CMOS logic circuits; Circuit optimization; Circuit synthesis; Compaction; Electrical capacitance tomography; Integrated circuit interconnections; Libraries; Rails; Routing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409219

Filename

409219