Virtual hardware and the limits of computational speed-up

This paper investigates the limits of achievable computational speed-up using available FPGA-based virtual hardware platforms as examples. It is shown that even if the additional hardware area is limited to only a 100% increment over the size of a realistic future general purpose processor, the virtual platform would still be able to exploit enough of the available algorithmic concurrency to push the overall task speed-up sufficiently close to its theoretical maximum